1. Field
Exemplary embodiments of the present invention relate to a semiconductor memory device, and more particularly, to a shift circuit of the semiconductor memory device.
2. Description of the Related Art
While there is a need to increase the integration degree of semiconductors, it is also desirable to increase their operation speeds. Available high-speed synchronous memories are synchronous dynamic random access memory (DRAM), double data rate (DDR) synchronous DRAM (SDRAM), RAMBUS DRAM, etc.
Here, a synchronous memory denotes a memory synchronized with an external system clock in operation. For example, a SDRAM operates in synchronization with a rising edge of a clock to allow one data input/output in response to each clock cycle. DDR SDRAM operates in synchronization with a falling edge as well as a rising edge of a clock to allow two data input/output in response to each clock cycle.
Generally, various operation timings are set for smooth data transmission in a semiconductor memory device such as a DDR SDRAM. According to an example of an operation timing, a write latency (WL) denotes a timing in which data inputs after a write command inputs. The write latency is based on a period of an external clock signal. Here, when the write latency is 4, data is inputted after four clock cycles from the time that the write command is applied.
According to another example of an operation timing in a semiconductor memory device, an additive latency (AL) is used. Here, when AL is not defined and an active signal is applied, read/write commands are applied after a time equal to tRCD passes from the input of the active signal. Here, tRCD denotes random address strobe (RAS) to column address strobe (CAS) delay. When AL is defined, the read/write commands can be applied before tRCD passes from the time that an RAS is applied. If AL is 2, the read/write commands in some circumstances may be applied 2 clock cycles before applying the read/write commands. Use of AL increases the utilization efficiency of data buses.
In case that a memory uses AL, a read latency (RL) is to be the sum of AL and column address strobe (CAS) latency (CL). Here, CL is the time from input of the read command to output of data in response to the read command.
As described above, in order to input/output data after the input of the application of read/write commands with appropriate delays, the applied read/write commands are to be shifted (that is, delayed) for an appropriate number of times corresponding to the delays. Here, the read/write commands are shifted until they are ready to be applied for input/output of data in response to the applied read/write commands. Here, in shifting write/read commands, a mode resister set (MRS) stores information as to how many times applied read/write commands are to be shifted. In response to the information stored in the MRS, a shift circuit shifts the applied read/write commands.
The shift circuit shifts and outputs input address as well as input commands in response to the information stored in the MRS. The structure and operation of a conventional shift circuit are as follows.
FIG. 1 illustrates a block diagram of a conventional shift circuit of a semiconductor device.
As can be seen from FIG. 1, a shift circuit includes a plurality of shifters 101-110 connected in series. Each of the shifters receives and shifts its input signal in response to a clock CLK.
In illustrating operations of the FIG. 1 circuit, consider the following situation where the number of the plurality of shifters 101, 102 and 110 in the shift circuit is 10, an input signal IN is a write command, and a write latency set by the MRS is 7. Since the write latency is 7, the shift circuit shifts and outputs the write command for 7 clock cycles. Here, a command is a signal with a pulse duration of 1 clock cycle or a half clock cycle, where the write command is a signal with a pulse duration of 1 clock cycle. The plurality of shifters 101-110 may each be a D-type flip-flop that delays and outputs its input after one clock cycle. A reset signal RST indicates a signal to reset the plurality of shifters 101-110.
When the write command is received as input signal IN, a first shifter 101 shifts the write command by one clock cycle and generates the shifted write command as a first positive output QR1 in response to the clock CLK. A second shifter 102 shifts the first positive output QR1 by one clock cycle and generates the shifted first positive output QR1 as a second positive output QR2 in response to the clock CLK. In the same way, each of shifters 103-110 shifts its input signal by one clock cycle and generates a shifted output in response to the clock CLK. Thus, the first to tenth shift circuits 101-110 each shift and generate the input write command by 1 clock cycle. Since the write latency is 7, data is outputted in response to a positive output QR7 of a seventh shifter 107 (not shown).
Alternatively, a negative output QF7 of the seventh shifter 107 may be used for controlling the data output. Delay values of negative outputs QF1-QF10 are smaller than 1 clock cycle compared to a corresponding input of the respective shifter and have a phase that is the inverse of the input signal IN.
It may be useful to have each of the shifters to operate, for example, only while its input signal is inputted, shifted and outputted and still allow some margins for the operation. However, the conventional shift circuit provides the clock CLK to all of the shifters 101-110. Thus, current flowing in the shift circuit and power consumption may unnecessarily increase.